Skip to main content

Department of Engineering and Communication

Frequently Asked Questions - FPGA Vision Remote Lab

Send us your questions about the FPGA Vision Remote Lab and we will update this page. Scroll down for impressum and privacy information.
QUESTION: Which FPGAs are accessible?
  • Altera Cyclone 10: 10CL120ZF484I8G (60 nm CMOS technology)
  • Altera Cyclone V: 5CEBA2F17C6 (28 nm CMOS technology)
  • Altera Cyclone IV: EP4CE22E22C7 (60 nm CMOS technology)

More information on selecting an FPGA experiment.

QUESTION: Which FPGA-Design software is required?

You require the free Quartus Prime Lite Edition, Release 21.1 (or earlier) from with this options:

  • Quartus Prime (includes Nios II EDS)
  • Questa-Intel FPGA Edition (includes Starter Edition)
  • Cyclone V and/or IV device support (one device is required, install both to compare FPGAs)
QUESTION: Where do I find the binary bitfile for upload to the remote lab?

Go to the directory of the FPGA project. There you find the subdirectory "output_files" and inside that subdirectory is a file with the suffix ".sof". This is the binary bitfile for upload to the remote lab.

The size of the bitfile depends on the target FPGA. For the Cyclone V 5CEBA2F17C6 it is 2385 KB. For the Cyclone IV EP4CE22E22C7 it is 688 KB.

QUESTION: How long takes processing in the remote-lab?

The remote-lab needs about 15 seconds for the experiment. If you have a slow internet connection add some time for the transfer of bitfile and images. The messages on the screen show you the progress of the experiment. We compress the images with JPEG in order to reduce bandwidth.

In the demo-mode you have two minutes per access, as a registered user you have five minutes. You can not extend this time once an experiment has started, but you can immediately reserve the experiment again.

QUESTION: Video or Image? What input is used?

The FPGA receives a video input in 720p format, that is a 1280x720 image with 60Hz frame-rate. The clock frequency is 74.25 MHz.

The content of the video signal is static, so it is always the same image that is given each frame. You can select images and upload your own image. This image will be given to the FPGA with 60Hz, so 60 times a second.

The output of the FPGA is again a 720p video and it is sampled with a frame-grabber. So the FPGA gives 60 images per second, and one of these images is shown in the remote-lab. With "Update Output Image" you can receive a new frame.

For many algorithms, like edge detection, processing always the same image is beneficial, as you can compare different versions of your design. For the future, we plan to have a video sequence as an option.

QUESTION: The experiment page shows the output image "No Signal". What is wrong?

The frame grabber at the output of the FPGA board does not receive a valid image signal with proper clock and sync signals.

Did you assign the pin locations for the FPGA? Check the critical warnings in the Quartus software. Do you have the message "No exact pin location assignment(s) for 63 pins of 63 total pins"? Perform "Assignments" -> "Import Assignments".

Otherwise, check the VHDL code. Synchronization requires the four output signals: clk_o, vs_out, hs_out, de_out.

QUESTION: Can I see the output image in full resolution?

Yes, click on the image and open it with full resolution.

QUESTION: Which input images are available?

The remote-lab can provide ten different images, all in 1280x720 pixel. Switch between the images with the controls above the input image. The images show:

  1. Motorway in Germany
  2. Motorway in Germany
  3. Road in Germany
  4. Road in Germany
  5. Road on Canary Islands, Spain
  6. Road in Andes mountains, Argentina
  7. Road in Germany, difficult for lane detection because of poor road markings
  8. Bridge in Denmark, difficult for lane detection because of poor visibility due to rain
  9. Test card with lower switching activity that should result in lower dynamic power consumption
  10. Here you can upload your own JPEG image, recommended resolution is 1280x720 pixel
QUESTION: How do I measure the power consumption of the FPGA?

An FPGA has two power supplies, one for the processing core, the other for the I/O-pins. We measure the current for the processing core, because this corresponds to the power consumption of the digital logic. Multiply the current with the supply voltage to get the consumed power.

QUESTION: How do I use the slide switches of the FPGA board?

The FPGA is connected to three switches which can be set to 1 and 0. These values correspond to the input "enable_in(2:0)" of the VHDL code.

QUESTION: Can I use Verilog for programming the FPGAs?

Yes, no problem. You upload the SOF-binary and you can use Verilog, different IP-cores and tools like Matlab/Simulink. Please check the provided VHDL source files or the lecture video "FPGA Vision - Circuit Design" for the I/O-interface.

QUESTION: What languages are available?

The lectures are in English and we provide captions in English for all lectures. For selected lectures we have subtitles in Arabic, Spanish, Ukrainian, Brazilian Portuguese. If you are lecturer for digital circuit design and want to translate subtitles to another language, please contact us.

The remote-lab is based on WebLab-Deusto and supports: Deutsch, English, Español, Euskara, Français, Magyar, Nederlands, Português, Româna, Slovencina, Ceština, Russian, Arabic.

Privacy of the FPGA Vision Remote Lab

For general information please see the data privacy statement of our webpage.

There are additional information for the FPGA remote-lab:

QUESTION: Which data do you store about me?

When you register for the remote-lab, we store the data that you provide there. When you perform an experiment, we store additional information. You can see your profile at the link in the right top corner of the remote-lab web page.

We also store cookies on your computer, so that our server can identify your access to experiments.

QUESTION: Which information do you store about my experiments?

We store accesses to the remote-lab with IP address and corresponding geographical position. When you perform an experiment you give commands to the remote-lab and can upload FPGA binaries and image files. This data is used to perform the experiment and logged. You can review this information in your profile. We use this information for academic evaluation of the remote-lab.

We reserve the right to perform an automatic analysis of the experiment data for academic evaluation. We also reserve the right to use experiment data to perform debugging of our remote-lab.

By using the remote-lab you agree that we store the data you provide.

QUESTION: How to correct, modify or remove data that is stored about me in the remote-lab?

Please contact us (see top of page) and we will take care of your request.

Datenschutz für das FPGA Vision Remote Lab

Die Datenschutzerklärung für die Hochschule finden Sie im Link der Fusszeile sowie hier:

Die folgenden zusätzlichen Informationen gelten für das Remote-Lab:

Frage: Welche Daten werden über mich als Nutzer/in gespeichert?

Wenn Sie sich für das Remote-Lab registrieren, speichern wir die Daten, die Sie dort angeben. Wenn Sie ein Experiment durchführen, speichern wir zusätzliche Informationen. Sie können Ihr Profil mit den gespeicherten Daten jederzeit über den Link in der rechten oberen Ecke der Remote-Lab-Webseite einsehen.

Auf Ihrem Rechner werden Cookies (kleine Datenpakete) gespeichert, damit unser Server Ihre Versuchsdaten zuordnen kann.

Frage: Welche Daten werden gespeichert, wenn ich ein Experiment durchführe?

Wir speichern Zugriffe auf das Remote-Lab mit IP-Adresse und entsprechender geografischer Position. Wenn Sie ein Experiment durchführen, geben Sie dem Remote-Lab Befehle und können FPGA-Binärdateien und Bilder hochladen. Diese Daten werden verwendet, um das Experiment durchzuführen und protokolliert. Sie können diese Informationen in Ihrem Profil einsehen. Wir verwenden diese Informationen für die wissenschaftliche Forschung zum Remote-Lab.

Wir behalten uns das Recht vor, eine automatische Analyse der Versuchsdaten für die wissenschaftliche Forschung durchzuführen. Wir behalten uns außerdem das Recht vor, die übermittelten Daten zu verwenden, um die Funktion unseres Remote-Lab zu überprüfen und Debugging durchzuführen.

Durch die Nutzung des Remote-Lab stimmen Sie zu, dass wir die von Ihnen bereitgestellten Daten speichern.

Frage: Wie kann ich für das Remote-Lab Daten berichtigen, löschen oder sperren lassen?

Bitte kontaktieren Sie uns (siehe Email-Adresse oben) und wir kümmern uns um Ihre Anfrage.

fpga-vision_small.png (DE)